The present invention relates generally to integrated circuits, and in particular to latches.
An integrated circuit includes a number of circuits connected together. Each of the circuits performs a particular task which, together with the tasks from other circuits, form a whole function of the integrated circuit. Some tasks involve processing a signal such as a data signal. Processing the data signal often requires a latching function for receiving the data signal and holding it for a certain period of time before passing it to another circuit within the integrated circuit. To ensure that the data signal is correctly received or latched, a companion signal such as a clock signal is normally sent along with the data signal to trigger or activate the latch. A typical latch has a data-to-clock setup and hold time. Setup time is the amount of time that a data signal must be present before a clock signal arrives. Hold time is the amount of time that the data signal is held valid after the clock signal has arrived. Setup and hold time occupy a portion of available time to latch the data. Therefore, the smaller the setup and hold time the better for the latch.
Setup and hold time is a function of the difference between the data and the clock paths to the latch element. In a typical latch, the clock and data paths do not have matching elements, which results in a large amount of setup and hold time. This reduces the available time to latch the data signal.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved latch.